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    <title>Tyrone Marhguy - Writing</title>
    <link>https://tmarhguy.com/writing/</link>
    <description>Writing on hardware projects by Tyrone Marhguy.</description>
    <language>en-us</language>
    <lastBuildDate>Mon, 03 Aug 2026 12:00:00 GMT</lastBuildDate>
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      <title>Reassessing Mac for optimization</title>
      <link>https://tmarhguy.com/writing/2026-08-03-reassessing-mac-for-optimization/</link>
      <description>Returning to the MAC tapeout path after months on Tomato — planning LibreLane flow, cross-verification, and timing closure.</description>
      <category>16-bit MAC Unit (Sky130)</category>
      <pubDate>Mon, 03 Aug 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Designing Additional Boards</title>
      <link>https://tmarhguy.com/writing/2026-08-02-designing-additional-boards/</link>
      <description>I am pushing to design the remaining boards. I had assumed that the most complicated one to design was the main board — the ALU — which is done and routed (07_alu). The next thi...</description>
      <category>Tomato CPU</category>
      <pubDate>Sun, 02 Aug 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Successful Synthesis - Implementation - Bitstream</title>
      <link>https://tmarhguy.com/writing/2026-08-02-successful-synthesis-implementation-bitstream/</link>
      <description>First clean Vivado build for the Nexys A7 ITCH pipeline — synthesis, implementation, and bitstream with USE_ETH=1.</description>
      <category>NASDAQ ITCH Hardware Parser</category>
      <pubDate>Sun, 02 Aug 2026 12:00:00 GMT</pubDate>
      <guid isPermaLink="true">https://tmarhguy.com/writing/2026-08-02-successful-synthesis-implementation-bitstream/</guid>
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    <item>
      <title>ITCH Ethernet Lab Bring-Up</title>
      <link>https://tmarhguy.com/writing/2026-08-01-itch-ethernet-lab-bring-up/</link>
      <description>Preparing Nexys A7 Ethernet ingress for end-to-end Mold/ITCH UDP testing on the FPGA market-data pipeline.</description>
      <category>NASDAQ ITCH Hardware Parser</category>
      <pubDate>Sat, 01 Aug 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Shell UI - Mango</title>
      <link>https://tmarhguy.com/writing/2026-08-01-shell-ui-mango/</link>
      <description>As the toolkit expands, remembering individual script paths, names, and arguments becomes cumbersome. To solve this, I am introducing Mango—a centralized, interactive shell inte...</description>
      <category>Mango Tools</category>
      <pubDate>Sat, 01 Aug 2026 12:00:00 GMT</pubDate>
      <guid isPermaLink="true">https://tmarhguy.com/writing/2026-08-01-shell-ui-mango/</guid>
    </item>
    <item>
      <title>Tools</title>
      <link>https://tmarhguy.com/writing/2026-08-01-tools/</link>
      <description>This project is a centralized, offline repository designed to replace SaaS platforms (like iLovePDF and online image compressors) entirely. By housing my most frequently used ut...</description>
      <category>Mango Tools</category>
      <pubDate>Sat, 01 Aug 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Falling back to 32b</title>
      <link>https://tmarhguy.com/writing/2026-07-31-falling-back-to-32b/</link>
      <description>In a rather if not seemingly swing between implementations, I have reconsidered and am falling back to the 32b design. The 40b redesign was intellectually clean — one word type,...</description>
      <category>Tomato CPU</category>
      <pubDate>Fri, 31 Jul 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>The lingering thoughts</title>
      <link>https://tmarhguy.com/writing/2026-07-31-the-lingering-thoughts/</link>
      <description>The ALU is routed and ready for PCB fabrication. That was the hardest slice of the datapath — three-operand LUT3, carry select, the full combinational core. The lingering proble...</description>
      <category>Tomato CPU</category>
      <pubDate>Fri, 31 Jul 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Redesign into 40b (Old design = 32b)</title>
      <link>https://tmarhguy.com/writing/2026-07-30-redesign-into-40b-old-design-32b/</link>
      <description>After roughly three months working on Tomato32, the recurring bottleneck has been instruction width, not the ALU itself. Convention says a 32-bit machine gets a 32-bit instructi...</description>
      <category>Tomato CPU</category>
      <pubDate>Thu, 30 Jul 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>Architecture Upgrade</title>
      <link>https://tmarhguy.com/writing/2026-07-13-architecture-upgrade/</link>
      <description>The sheer constraint posed by area and available hardware imply that designs that offer more for less are favourable, unlike conventional metrics like parasitic and wiring budge...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 13 Jul 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Demo Ideas</title>
      <link>https://tmarhguy.com/writing/2026-07-13-demo-ideas/</link>
      <description>It quickly gets abstracted and perhaps indistinguishable from a black box if the final design has no reasonably impressive demo. I&apos;ve considered a lot of ideas ranging from mode...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 13 Jul 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Downgrade for an upgrade - 32b to 16b x 4</title>
      <link>https://tmarhguy.com/writing/2026-07-13-downgrade-for-an-upgrade-32b-to-16b-x-4/</link>
      <description>This ALU has taken several routes since the first abstractions. In the most recent version before this change, I wanted to wire 8 cells of 4b each into a 32b cell. The catch is ...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 13 Jul 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>Pipelined FPGA - What if...</title>
      <link>https://tmarhguy.com/writing/2026-07-13-pipelined-fpga-what-if/</link>
      <description>After observing, time is but a monotonic quantity and universal. In current FPGA designs, we program and use, and for another use case, we repeat, In future tomato designs, I am...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 13 Jul 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>Truth Table Latch</title>
      <link>https://tmarhguy.com/writing/2026-07-13-truth-table-latch/</link>
      <description>In the current design, the individual cells of tomato may not seem to undergo reprogramming for each operation, given the philosophy it was based off of: what if computers had t...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 13 Jul 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>Elimination of Mode Multiplexers</title>
      <link>https://tmarhguy.com/writing/2026-06-27-elimination-of-mode-multiplexers/</link>
      <description>Initial State &amp; Bottleneck: The previous ALU design utilized a parallel execution model. An incoming signal would split: one path raced through the A/B masking logic into the 74...</description>
      <category>Tomato CPU</category>
      <pubDate>Sat, 27 Jun 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>ALU Architecture Refinement &amp; Logic Optimization</title>
      <link>https://tmarhguy.com/writing/2026-06-26-alu-architecture-refinement-logic-optimization/</link>
      <description>Refinement of Generate ($G$) and Propagate ($P$) Signals In the initial architecture, the logic generation for the 74182 look-ahead unit was bottlenecked by a naïve implementati...</description>
      <category>8-bit Discrete Transistor ALU</category>
      <pubDate>Fri, 26 Jun 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>ALU - Redesign with 74251</title>
      <link>https://tmarhguy.com/writing/2026-06-26-alu-redesign-with-74251/</link>
      <description>In routing the ALU, I came across a realization that the fact that the 125 + 138 combination defeats the optimization i was looking for. In fact, I need 3 chips for a single ALU...</description>
      <category>8-bit Discrete Transistor ALU</category>
      <pubDate>Fri, 26 Jun 2026 12:00:00 GMT</pubDate>
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    </item>
    <item>
      <title>ALU segment display design</title>
      <link>https://tmarhguy.com/writing/2026-06-19-alu-segment-display-design/</link>
      <description>Four 32-bit values on screen at once—the three LUT3 operand buses plus the ALU writeback. Each row is eight hex digits; thirty-two seven-segment displays total, live as the data...</description>
      <category>8-bit Discrete Transistor ALU</category>
      <pubDate>Fri, 19 Jun 2026 12:00:00 GMT</pubDate>
      <guid isPermaLink="true">https://tmarhguy.com/writing/2026-06-19-alu-segment-display-design/</guid>
    </item>
    <item>
      <title>Microcode Control Modularization</title>
      <link>https://tmarhguy.com/writing/2026-06-16-microcode-control-modularization/</link>
      <description>The microcode ROM was always going to be a wiring problem. Every instruction looks up a 64-bit control word: what the ALU should do, whether to write a register, read memory, ju...</description>
      <category>Tomato CPU</category>
      <pubDate>Tue, 16 Jun 2026 12:00:00 GMT</pubDate>
      <guid isPermaLink="true">https://tmarhguy.com/writing/2026-06-16-microcode-control-modularization/</guid>
    </item>
    <item>
      <title>Multiplication and Division</title>
      <link>https://tmarhguy.com/writing/2026-06-15-multiplication-and-division/</link>
      <description>One of the biggest hurdles in this build has been implementing hardware multiplication and division. The standard naive approach—sequencing operations to `shift -&gt; add -&gt; accumu...</description>
      <category>Tomato CPU</category>
      <pubDate>Mon, 15 Jun 2026 12:00:00 GMT</pubDate>
      <guid isPermaLink="true">https://tmarhguy.com/writing/2026-06-15-multiplication-and-division/</guid>
    </item>
    <item>
      <title>Load Store Pipeline Analysis</title>
      <link>https://tmarhguy.com/writing/2026-06-11-load-store-pipeline-analysis/</link>
      <description>Every opcode indexes a 48-bit word in the microcode ROM (`DIG_ROM_256X48_microcodeeeprom`). The fields, confirmed from `main.v:2087–2106`: | Bits | Field | Notes | |------|-----...</description>
      <category>Tomato CPU</category>
      <pubDate>Thu, 11 Jun 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Implementing Mul-Div Engine</title>
      <link>https://tmarhguy.com/writing/2026-06-10-implementing-mul-div-engine/</link>
      <description>Today&apos;s goal is integrating the multiply-divide engine. I am considering a few ideas. 74xx284/85 can compute the lower and upper products, so I will use them and sequence to com...</description>
      <category>Tomato CPU</category>
      <pubDate>Wed, 10 Jun 2026 12:00:00 GMT</pubDate>
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    <item>
      <title>Welcome to Tomato 32</title>
      <link>https://tmarhguy.com/writing/welcome-to-tomato-32/</link>
      <description>This is a build log for Tomato 32. It will keep track of the questions that come up and the answers I settled for. It focussed on build log, the constraints explored and the jou...</description>
      <category>Tomato CPU</category>
      <pubDate>Fri, 01 Aug 2025 12:00:00 GMT</pubDate>
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