Tyrone Marhguy
- I build computer systems from discrete MOSFETs through full ASIC tapeout.
Computer Engineering junior at the University of Pennsylvania specializing in computer architecture, RTL design, and hardware verification. I thrive at the intersection of hardware and software—architecting boards, writing SystemVerilog, and building the constrained-random environments that prove them. - Open Source Contributions: Writing core C++/Python patches for open-source EDA tools (Verilator, LibreLane, OpenROAD, OpenFPGA), including fixes shipped in the LibreLane 3.0.8 and 3.0.10 releases.
- The Builds: Discrete 32-bit Polymorphic Dual-LUT3 CPU (Tomato), a 100 Mbps UDP/IP stack, a NASDAQ ITCH 5.0 FPGA parser, a 3,488 MOSFET ALU, a Sky130 BFloat16 MAC, and a full-custom 22nm SRAM. All proven with UVM, cocotb, and formal verification against millions of test vectors.
- The Work: Hardware Research Engineer (Fall 2026) at Fluid Silicon (RTL & Emulation) and Software Engineer at Aragorn AI. Previously Hardware & Firmware Engineer at Vero Electric (PCB design & Board bring-up).
Selected work
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Tomato — Discrete 32-bit Polymorphic Dual-LUT3 CPU
8-board Discrete 32-bit Polymorphic Dual-LUT3 CPU from discrete logic through PCB tapeout; FPGA prototype at 58 MHz with SymbiYosys formal verification.
16×4 SRAM — Full-Custom Analog Design
Full-custom 6T SRAM macro in 22 nm HP with clocked StrongARM sense amp; 4.571 GHz f_max with NGSpice functional readback.
100 Mbps UDP/IP Stack
Deterministic 100 Mbps RMII pipeline — MAC, ARP/IP/UDP on Nexys A7 Artix-7; sub-200 ns RX-to-TX loopback with 100% cocotb coverage.
From the bench
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AS6C62256 has 15 address bits — Tomato exposes all of them: 32,768 GPR. Half a Blackwell SM.
Tomato works beautifully!
HDMI GUI on the TV — 2,300+ lines of TomatoOS. Tetris, Snake, Racer, Fibonacci. Keyboard matrix next; chip tapeout on the horizon.
Successful Video — FPGA + PMOD
PMOD 12-bit DVI soldered and flashed. Red, green, blue, gray bars on HDMI. Pixels on the glass.