From the transistor to the terminal. Computers, circuits, and tools I wanted to exist—so I started building them.
Custom 32-bit architecture with a working FPGA computer, assembler, and TomatoOS over HDMI. Discrete ALU board fabricated; the complete discrete machine is in progress.
SystemVerilog · UVM · SymbiYosys · KiCad
Standalone programmable 3D GPU — vertex/fragment shaders, rasterizer, depth, texture, double-buffered 320×180; pineapple and cube both rendered on silicon via FOSS Yosys/nextpnr flow.
Verilog · Yosys/nextpnr · Artix-7 · DVI
Hybrid CMOS ALU design: 624 discrete MOSFETs plus 2,864 transistors inside 74HC logic. Schematics, PCB layout, and 1.24M automated simulation vectors.
Discrete Transistors · KiCad · Python · Formal Verification
RV64IMAC; 2-wide fetch/decode/issue/commit with gshare + BTB + RAS, AXI4-Lite memory, Verilator + cocotb + riscv-tests with Yosys/OpenLane2 feasibility.
SystemVerilog · RISC-V · AXI4-Lite · Verilator · cocotb
BFloat16 MAC with FP32 accumulator and 4-cycle streaming I/O; cocotb-verified RTL with a local LibreLane flow targeting SkyWater 130 nm. Shuttle submission is a later milestone.
SystemVerilog · LibreLane · Sky130 · cocotb
Deterministic 100 Mbps RMII pipeline — MAC, ARP/IP/UDP on Nexys A7 Artix-7; sub-200 ns RX-to-TX loopback with 100% cocotb coverage.
SystemVerilog · RMII · cocotb · AXI4-Stream
Full-custom 6T SRAM macro in 22 nm HP with clocked StrongARM sense amp; 4.571 GHz f_max with NGSpice functional readback.
Electric VLSI · NGSpice · Python
Streaming 8-bit FSM decodes ITCH 5.0 with cocotb golden-model verification; dual-sided 512-entry BRAM limit book on Artix-7 at 100 MHz.
SystemVerilog · Vivado · cocotb · Verilator
ESE 3700 full-adder study — baseline vs. delay-optimized 8-bit RCA in 22 nm HP with TG-XOR2, alternating carry polarity, and six-metric SPICE characterization (~55% delay reduction).
Electric VLSI · NGSpice · LaTeX
Python pipeline driving NGSpice runs with binary-search F_max convergence; automated parametric sweeps and comparative statistical reports.
Python · NGSpice · C++
Transactional database built from first principles in Rust — ordered key-value storage, a checksummed WAL, WAL-backed memtables, immutable SSTables, LSM flush/merge, manifests, compaction, crash recovery, and correctness testing. Growing toward MVCC and distributed transactions.
Rust · LSM · WAL · Tokio
Offline video, PDF, and image conversion behind a `mango` terminal menu — now a system-wide call from any working directory, not locked to the repo path.
Bash · Python · FFmpeg · Ghostscript
FastAPI + PostgreSQL service ingesting Vivado and OpenLane synthesis PPA metrics; Dockerized with Pytest-covered ingestion pipeline.
Python · FastAPI · PostgreSQL · Docker
Client-side image compression using truncated SVD: upload an image and adjust its rank to compare detail, reconstruction error, and file size. Web Workers and caching keep decomposition off the main thread.
TypeScript · React · Web Workers · Linear Algebra
Fixes chk.rpt so pre- and post-synth errors both count; shipped as 3.0.10 · #1016Fixes Yosys ≥ 0.68 abc -fast so synthesis does not die; shipped as 3.0.8 · #1015
Fixes MINWIDTH WRONGDIRECTION so production LEF files load · #11107
Fixes Linux peak-memory stats so --stats matches real RSS · #8070
Fixes the contributor guide link so new contributors land in the right place · #2682Fixes directlist interconnect docs so syntax matches the parser · #2683
